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3 V LVDS Quad CMOS Differential Line Receiver ADN4668
FEATURES
15 kV ESD protection on receiver input pins 400 Mbps (200 MHz) switching rates Flow-through pin configuration simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay 3.3 V power supply High impedance outputs on power-down Low power design (3 mW quiescent typical) Interoperable with existing 5 V LVDS drivers Accepts small swing (310 mV typical) differential input signal levels Supports open, short, and terminated input fail-safe 0 V to -100 mV threshold region Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range of -40C to +85C Available in low profile TSSOP package
FUNCTIONAL BLOCK DIAGRAM
VCC
ADN4668
RIN1+ RIN1- RIN2+ RIN2- RIN3+ RIN3- RIN4+ RIN4- EN
07237-001
R1
ROUT1
R2
ROUT2
R3
ROUT3
R4
ROUT4
EN GND
Figure 1.
APPLICATIONS
Point-to-point data transmission Multidrop buses Clock distribution networks Backplane receivers
GENERAL DESCRIPTION
The ADN4668 is a quad-channel CMOS, low voltage differential signaling (LVDS) line receiver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flowthrough pin configuration for easy PCB layout and separation of input and output signals. The device accepts low voltage (310 mV typical) differential input signals and converts them to a single-ended, 3 V TTL/CMOS logic level. The ADN4668 also offers active-high and active-low enable/disable inputs (EN and EN) that control all four receivers. They disable the receivers and switch the outputs to a high impedance state. This high impedance state allows the outputs of one or more ADN4668s to be multiplexed together and reduces the quiescent power consumption to 3 mW typical. The ADN4668 and its companion driver, the ADN4667, offer a new solution to high speed, point-to-point data transmission and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADN4668 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Characteristics........................................................................ 4 Test Circuits and Waveforms ...................................................... 4 Absolute Maximum Ratings............................................................ 6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Typical Performance Characteristics ..............................................8 Theory of Operation ...................................................................... 11 Enable Inputs .............................................................................. 11 Applications Information.......................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 12
REVISION HISTORY
3/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4668 SPECIFICATIONS
VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. 1, 2 Table 1.
Parameter Min Typ -35 -35 5 1 1 Max 0 2.3 +10 +10 +20 VCC 0.8 +10 Unit mV mV V A A A V V A V V V V V V A mA mA kV kV Conditions/Comments VCM = 1.2 V, 0.05 V, 2.95 V VCM = 1.2 V, 0.05 V, 2.95 V VID = 200 mV p-p VIN = 2.8 V, VCC = 3.6 V or 0 V VIN = 0 V, VCC = 3.6 V or 0 V VIN = 3.6 V, VCC = 0 V
LVDS INPUTS (RINx+, RINx-)
Differential Input High Threshold, VTH at RINx+, RINx- 3 Differential Input Low Threshold, VTL at RINx+, RINx-3 Common-Mode Voltage Range, VCMR at RINx+, RINx- 4 Input Current, IIN at RINx+, RINx- -100 0.1 -10 -10 -20 2.0 GND -10 -1.5 2.7 2.7 2.7 -15 -10
Input High Voltage, VIH Input Low Voltage, VIL Input Current, II Input Clamp Voltage, VCL
5 -0.8 3.3 3.3 3.3 0.05 -47 1 12 1 15 3.5
VIN = 0 V or VCC, other input = VCC or GND ICL = -18 mA IOH = -0.4 mA, VID = 200 mV IOH = -0.4 mA, input terminated IOH = -0.4 mA, input shorted IOL = 2 mA, VID = -200 mV Enabled, VOUT = 0 V Disabled, VOUT = 0 V or VCC EN = VCC, inputs open EN = GND, inputs open Human body model Human body model
OUTPUTS (ROUTx)
Output High Voltage, VOH
Output Low Voltage, VOL Output Short-Circuit Current, IOS 5 Output Off State Current, IOZ
0.25 -100 +10 15 5
POWER SUPPLY
No Load Supply, Current Receivers Enabled, ICC No Load Supply, Current Receivers Disabled, ICCZ ESD PROTECTION RINx+, RINx- Pins All Pins Except RINx+, RINx-
1
Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified. All typicals are given for VCC = 3.3 V and TA = 25C. 3 VCC is always higher than the RINx+ and RINx- voltage. RINx- and RINx+ have a voltage range of -0.2 V to VCC - VID/2. However, to be compliant with ac specifications, the common voltage range is 0.1 V to 2.3 V. 4 VCMR is reduced for larger VID. For example, if VID = 400 mV, VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported over the common-mode range of 0 V to 2.4 V but is supported only with inputs shorted and no external common-mode voltage applied. VID up to VCC - 0 V can be applied to the RINx+/RINx- inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications apply for 200 mV VID 800 mV over the common-mode range. 5 Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Only one output should be shorted at a time; do not exceed the maximum junction temperature specification.
2
Rev. 0 | Page 3 of 12
ADN4668
AC CHARACTERISTICS
VDD = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted. 1, 2, 3, 4 Table 2.
Parameter 5 Differential Propagation Delay, High-to-Low, tPHLD Differential Propagation Delay, Low-to-High, tPLHD Differential Pulse Skew |tPHLD - tPLHD|, tSKD1 8 Differential Channel-to-Channel Skew, Same Device, tSKD23 Differential Part-to-Part Skew, tSKD34 Differential Part-to-Part Skew, tSKD4 9 Rise Time, tTLH Fall Time, tTHL Disable Time, High-to-Z, tPHZ Disable Time, Low-to-Z, tPLZ Enable Time, Z-to-High, tPZH Enable Time, Z-to-Low, tPZL Maximum Operating Frequency, fMAX 10
1 2
Min 1.2 1.2 0 0
Typ 2.0 1.9 0.1 0.15
Max 2.7 2.7 0.4 0.5 1.0 1.5 1.0 1.0 14 14 14 14
Unit ns ns ns ns ns ns ns ns ns ns ns ns MHz
Conditions/Comments 6 CL = 15 pF, 7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 CL = 15 pF,7 VID = 200 mV, see Figure 2 and Figure 3 RL = 2 k, CL = 15 pF,7 see Figure 4 and Figure 5 RL = 2 k, CL = 15 pF,7 see Figure 4 and Figure 5 RL = 2 k, CL = 15 pF,7 see Figure 4 and Figure 5 RL = 2 k, CL = 15 pF,7 see Figure 4 and Figure 5 All channels switching
200
0.5 0.35 8 8 9 9 250
All typicals are given for VCC = 3.3 V and TA = 25C. Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 , tR and tF (0% to 100%) 3 ns for RINx+/RINx-. 3 Channel-to-channel skew, tSKD2, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. 4 Part-to-part skew, tSKD3, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same VCC and within 5C of each other within the operating temperature range. 5 AC parameters are guaranteed by design and characterization. 6 Current-into-device pins are defined as positive. Current-out-of-device pins are defined as negative. All voltages are referenced to ground, unless otherwise specified. 7 CL includes probe and jig capacitance. 8 tSKD1 is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel. 9 Part-to-part skew, tSKD4, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges and across process distribution. tSKD4 is defined as |maximum - minimum| differential propagation delay. 10 fMAX generator input conditions: f = 200 MHz, tR = tF < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V p-p). Output criteria: 60%/40% duty cycle, VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), load = 15 pF (stray plus probes).
TEST CIRCUITS AND WAVEFORMS
VCC
SIGNAL GENERATOR 50
RINx+ RINx- 50 RECEIVER IS ENABLED CL ROUTx
CL = LOAD AND TEST JIG CAPACITANCE
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
Rev. 0 | Page 4 of 12
07237-002
ADN4668
RINx- 0V (DIFFERENTIAL) RINx+ VID = 200mV 1.2V 1.1V 1.3V
tPLHD
tPHLD
VOH 80% 80% 1.5V 20%
ROUTx
1.5V 20%
tTLH
tTHL
VOL
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
VCC S1
RL RINx+ RINx- EN SIGNAL GENERATOR ROUTx CL
50 EN GND
NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. 2. S1 CONNECTED TO VCC FOR tPZL AND tPLZ MEASUREMENTS. 3. S1 CONNECTED TO GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 4. Test Circuit for Receiver Enable/Disable Delay
07237-004
07237-003
3V EN WITH EN = GND OR OPEN CIRCUIT 1.5V 1.5V 0V
3V EN WITH EN = VCC 1.5V 1.5V 0V
tPHZ
ROUTx WITH VID = +100mV
0.5V
tPZH
50%
VOH
GND
VCC ROUTx WITH VID = -100mV 0.5V 50%
07237-005
tPLZ
tPZL
VOL
Figure 5. Receiver Enable/Disable Delay Waveforms
Rev. 0 | Page 5 of 12
ADN4668 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VCC to GND Input Voltage (RINx+, RINx-) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (ROUTx) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ MAX) Power Dissipation TSSOP Package JA Thermal Impedance Reflow Soldering Peak Temperature Pb-Free Rating -0.3 V to +4 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -40C to +85C -65C to +150C 150C (TJ MAX - TA)/JA 150.4C/W 260C 5C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 6 of 12
ADN4668 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RIN1- RIN1+ RIN2+ RIN2- RIN3- RIN3+ RIN4+ RIN4-
1 2 3 4 5 6 7 8 16 EN 15 ROUT1
ADN4668
TOP VIEW (Not to Scale)
14 ROUT2 13 VCC 12 GND 11 ROUT3 10 ROUT4
07237-006
9
EN
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic RIN1- RIN1+ RIN2+ RIN2- RIN3- RIN3+ RIN4+ RIN4- EN Description Receiver Channel 1 Inverting Input. When this input is more negative than RIN1+, ROUT1 is high. When this input is more positive than RIN1+, ROUT1 is low. Receiver Channel 1 Noninverting Input. When this input is more positive than RIN1-, ROUT1 is high. When this input is more negative than RIN1-, ROUT1 is low. Receiver Channel 2 Noninverting Input. When this input is more positive than RIN2-, ROUT2 is high. When this input is more negative than RIN2-, ROUT2 is low. Receiver Channel 2 Inverting Input. When this input is more negative than RIN2+, ROUT2 is high. When this input is more positive than RIN2+, ROUT2 is low. Receiver Channel 3 Inverting Input. When this input is more negative than RIN3+, ROUT3 is high. When this input is more positive than RIN3+, ROUT3 is low. Receiver Channel 3 Noninverting Input. When this input is more positive than RIN3-, ROUT3 is high. When this input is more negative than RIN3-, ROUT3 is low. Receiver Channel 4 Noninverting Input. When this input is more positive than RIN4-, ROUT4 is high. When this input is more negative than RIN4-, ROUT4 is low. Receiver Channel 4 Inverting Input. When this input is more negative than RIN4+, ROUT4 is high. When this input is more positive than RIN4+, ROUT4 is low. Active-Low Enable and Power-Down Input with Pulldown (3 V TTL/CMOS). When EN is held high, EN enables the receiver outputs when EN is low or open circuit and puts the receiver outputs into a high impedance state and powers down the device when EN is high. Receiver Channel 4 Output (3 V TTL/CMOS). If the differential input voltage between RIN4+ and RIN4- is positive, this output is high. If the differential input voltage is negative, this output is low. Receiver Channel 3 Output (3 V TTL/CMOS). If the differential input voltage between RIN3+ and RIN3- is positive, this output is high. If the differential input voltage is negative, this output is low. Ground Reference Point for All Circuitry on the Part. Power Supply Input. These parts can be operated from 3.0 V to 3.6 V. Receiver Channel 2 Output (3 V TTL/CMOS). If the differential input voltage between RIN2+ and RIN2- is positive, this output is high. If the differential input voltage is negative, this output is low. Receiver Channel 1 Output (3 V TTL/CMOS). If the differential input voltage between RIN1+ and RIN1- is positive, this output is high. If the differential input voltage is negative, this output is low. Active-High Enable and Power-Down Input (3 V TTL/CMOS). When EN is held low or open circuit, EN enables the receiver outputs when EN is high and puts the receiver outputs into a high impedance state and powers down the device when EN is low.
10 11 12 13 14 15 16
ROUT4 ROUT3 GND VCC ROUT2 ROUT1 EN
Rev. 0 | Page 7 of 12
ADN4668 TYPICAL PERFORMANCE CHARACTERISTICS
3.6 3.5 3.4 3.3 3.2 3.1 3.0 2.9
07237-007
-0.06
OUTPUT TRISTATE CURRENT, IOS (nA)
OUTPUT HIGH VOLTAGE, VOH (V)
ILOAD = -400A TA = 25C VID = 200mV
-0.07 -0.08 -0.09 -0.10 -0.11 -0.12 -0.13 -0.14 -0.15
VOUT = 0V TA = 25C
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 7. Output High Voltage, VOH, vs. Power Supply Voltage, VCC
Figure 10. Output Tristate Current, IOS, vs. Power Supply Voltage, VCC
0
33.60 33.55 33.50 33.45 33.40 33.35 33.30 33.25 3.0 3.1 3.2 3.3 3.4 3.5 3.6
07237-008
THRESHOLD VOLTAGE, VTH (mV)
OUTPUT LOW VOLTAGE, VOL (mV)
ILOAD = 2A TA = 25C VID = -200mV
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50 3.0
VOUT = 0V TA = 25C
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 8. Output Low Voltage, VOL, vs. Power Supply Voltage, VCC
-35
OUTPUT SHORT-CIRCUIT CURRENT, I OS (mA)
Figure 11. Threshold Voltage, VTH, vs. Power Supply Voltage (VCC)
100
-37 -39 -41 -43 -45 -47 -49 -51 -53 -55
POWER SUPPLY CURRENT, ICC (mA)
VOUT = 0V TA = 25C
90 80 70 60 50 40 30 20 10
07237-009
ALL CHANNELS SWITCHING
ONE CHANNEL SWITCHING
3.0
3.1
3.2
3.3
3.4
3.5
3.6
100k
1M
10M
100M
1G
POWER SUPPLY VOLTAGE, VCC (V)
BIT RATE (bps)
Figure 9. Output Short-Circuit Current, IOS, vs. Power Supply Voltage, VCC
Figure 12. Power Supply Current, ICC, vs. Bit Rate
Rev. 0 | Page 8 of 12
07237-012
0 10k
07237-011
07237-010
ADN4668
93.5 2.40
DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns)
POWER SUPPLY CURRENT, ICC (mA)
93.0 92.5 92.0 91.5 91.0 90.5 90.0 -40
VCC = 3.3V VID = 200mV FREQ = 200MHz ALL CHANNELS SWITCHING
2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 3.0 3.1 3.2 3.3 3.4
TA = 25C VID = 200mV FREQ = 200MHz CL = 15pF
tPHLD
tPLHD
07237-016
-15
10
35
60
85
07237-022
3.5
3.6
AMBIENT TEMPERATURE, TA (C)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 13. Power Supply Current, ICC, vs. Ambient Temperature (TA)
2.35
DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns)
Figure 16. Differential Propagation Delay, tPLHD, tPHLD, vs. Power Supply Voltage, VCC
8
DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns)
2.30 2.25 2.20 2.15 2.10 2.05 2.00 -40
VCC = 3.3V VID = 200mV FREQ = 200MHz CL = 15pF
7 6 5 4 3 2 1 0
TA = 25C FREQ = 200MHz VCM = 1.2V CL = 15pF
tPHLD tPLHD
tPLHD tPHLD
07237-017
-15
10
35
60
85
07237-014
0
500
1000
1500
2000
2500
3000
AMBIENT TEMPERATURE, TA (C)
DIFFERENTIAL INPUT VOLTAGE, VID (mV)
Figure 14. Differential Propagation Delay, tPLHD, tPHLD, vs. Ambient Temperature, TA
4.0
DIFFERENTIAL PROPAGATION DELAY, tPLHD , tPHLD (ns)
Figure 17. Differential Propagation Delay, tPLHD, tPHLD, vs. Differential Input Voltage, VID
200 TA = 25C VID = 200mV FREQ = 200MHz CL = 15pF
3.5
DIFFERENTIAL SKEW, tSKD (ps)
07237-015
TA = 25C FREQ = 200MHz VID = 200mV CL = 15pF
150 100 50 0 -50 -100
3.0
2.5
tPLHD
2.0
tPHLD
1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-200 3.0
3.1
3.2
3.3
3.4
3.5
3.6
COMMON-MODE VOLTAGE, VCM (V)
POWER SUPPLY VOLTAGE, VCC (V)
Figure 15. Differential Propagation Delay, tPLHD, tPHLD, vs. Common-Mode Voltage, VCM
Figure 18. Differential Skew, tSKD, vs. Power Supply Voltage, VCC
Rev. 0 | Page 9 of 12
07237-018
-150
ADN4668
80 60
DIFFERENTIAL SKEW, tSKD (ps)
560 VCC = 3.3V VID = 200mV FREQ = 200MHz CL = 15pF 550
TRANSITION TIME, tTLH, tTHL (ps)
540 530 520 510 500 490 480 470 460 450 -40
40 20 0 -20 -40
VCC = 3.3V VID = 200mV FREQ = 25MHz CL = 15pF
tTLH
07237-019
-80 -40
-15
10
35
60
85
-15
10
35
60
80
AMBIENT TEMPERATURE, TA (C)
AMBIENT TEMPERATURE, TA (C)
Figure 19. Differential Skew, tSKD, vs. Ambient Temperature, TA
550 540
TRANSITION TIME, tTLH, tTHL (ps)
Figure 21. Transition Time, tTLH, tTHL, vs. Ambient Temperature, TA
530 520 510 500 490 480
tTLH
TA = 25C VID = 200mV FREQ = 25MHz CL = 15pF
tTHL
07237-020
470 460 3.0 3.1 3.2 3.3 3.4 3.5
3.6
POWER SUPPLY VOLTAGE, VCC (V)
Figure 20. Transition Time, tTLH, tTHL, vs. Power Supply Voltage, VCC
Rev. 0 | Page 10 of 12
07237-021
-60
tTHL
ADN4668 THEORY OF OPERATION
The ADN4668 is a quad-channel line receiver for low voltage differential signaling. It takes a differential input signal of 310 mV typical and converts it into a single-ended 3 V TTL/CMOS logic signal. A differential current input signal, received via a transmission medium such as a twisted pair cable, develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 . The differential voltage is detected by the receiver and converted back into a single-ended logic signal. When the noninverting receiver input, RINx+, is positive with respect to the inverting input, RINx- (current flows through RT from RINx+ to RINx-), ROUTx is high. When the noninverting receiver input, RIN+, is negative with respect to the inverting input, RINx- (current flows through RT from RINx- to RINx+), ROUTx is low. Using the ADN4667 as a driver, the received differential current is between 2.5 mA and 4.5 mA (3.1 mA typical), developing between 250 mV and 450 mV across a 100 termination resistor. The received voltage is centered around the receiver offset of 1.2 V. In other words, the noninverting receiver input is typically (1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input is (1.2 V - [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the inverting and noninverting input voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. Current-mode signaling offers considerable advantages over voltage-mode signaling, such as the RS-422. The operating current remains fairly constant with increased switching frequency, whereas the operating current of voltage-mode drivers increases exponentially in most cases. This increase is caused by the overlap as internal gates switch between high and low, causing currents to flow from VCC to ground. A current-mode device reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emittercoupled logic (PECL), but without the high quiescent current of ECL and PECL.
ENABLE INPUTS
The ADN4668 has active-high and active-low enable inputs that put all the logic outputs into a high impedance state when disabled, reducing device current consumption from 9 mA typical to 1 mA typical. See Table 5 for a truth table of the enable inputs. Table 5. Enable Inputs Truth Table
EN EN RINx+ 1.045 V 1.355 V X RINx- 1.355 V 1.045 V X ROUTx 0 1 High-Z High Low or Open High Low or Open Any other combination of EN and EN
APPLICATIONS INFORMATION
Figure 22 shows a typical application for point-to-point data transmission using the ADN4667 as the driver and the ADN4668 as the receiver.
1/4 ADN4667 EN EN DOUTy+
DIN
1/4 ADN4668 EN EN RINx+
RT 100
DOUTy- RINx-
DOUT
07237-023
GND
GND
Figure 22. Typical Application Circuit
Rev. 0 | Page 11 of 12
ADN4668 OUTLINE DIMENSIONS
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 23. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
ORDERING GUIDE
Model ADN4668ARUZ 1 ADN4668ARUZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C
Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP]
Package Option RU-16 RU-16
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07237-0-3/08(0)
Rev. 0 | Page 12 of 12

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